As the design scale of integrated circuits (IC) continues to expand, the density of electronic devices on a single chip is growing, and the characteristic dimension of electronic devices is diminishing. As known in the art, the IC process flow contains many complex processes, and each process has a specific process deviation, which results in the yield reduction of IC chips. In the background of manufacturability, test chip is used to monitor and improve the yield of IC manufacture effectively, it is very effective to obtain the necessary data of manufacturing process and yield improvement through testing test chip.
Short-ranged test chip and addressable test chip are two types of the test chips frequently used in the manufacture of IC. Short-ranged test chip has been widely used because of its short production cycle, flexible test and high accuracy. However, in the traditional short-ranged test chip, each device under to test (DUT) needs to be connected to two or more pads, therefore, the disadvantage of short-ranged test chip is very obvious: low utilization rate of area. The addressable test chip uses decoders and the switching circuit to achieve the purpose of sharing pads between DUTs, but the type of test chip requires more complicated peripheral circuit. The simplification for the peripheral circuit for the addressable test chip has become the main problem to limit the wide application of the addressable test chip. A technical improvement about this problem has been mentioned in CN patent applications ZL201010612475.8, ZL 201520437526. 6 etc.